hardware acceleration Search Results


hardware acceleration units  (Qualcomm Inc)
90
Qualcomm Inc hardware acceleration units
Hardware Acceleration Units, supplied by Qualcomm Inc, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/hardware acceleration units/product/Qualcomm Inc
Average 90 stars, based on 1 article reviews
hardware acceleration units - by Bioz Stars, 2026-04
90/100 stars
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hardware accelerator  (ChaCha Search Inc)
90
ChaCha Search Inc hardware accelerator
Hardware Accelerator, supplied by ChaCha Search Inc, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/hardware accelerator/product/ChaCha Search Inc
Average 90 stars, based on 1 article reviews
hardware accelerator - by Bioz Stars, 2026-04
90/100 stars
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hardware accelerators  (Accelergy Corporation)
90
Accelergy Corporation hardware accelerators
Hardware Accelerators, supplied by Accelergy Corporation, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/hardware accelerators/product/Accelergy Corporation
Average 90 stars, based on 1 article reviews
hardware accelerators - by Bioz Stars, 2026-04
90/100 stars
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havac hardware accelerator  (Xilinx Inc)
90
Xilinx Inc havac hardware accelerator
Havac Hardware Accelerator, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/havac hardware accelerator/product/Xilinx Inc
Average 90 stars, based on 1 article reviews
havac hardware accelerator - by Bioz Stars, 2026-04
90/100 stars
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hardware accelerated version  (Verasonics Inc)
90
Verasonics Inc hardware accelerated version
Hardware Accelerated Version, supplied by Verasonics Inc, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/hardware accelerated version/product/Verasonics Inc
Average 90 stars, based on 1 article reviews
hardware accelerated version - by Bioz Stars, 2026-04
90/100 stars
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decypher ® accelerated hardware  (Timelogic)
90
Timelogic decypher ® accelerated hardware
Decypher ® Accelerated Hardware, supplied by Timelogic, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/decypher ® accelerated hardware/product/Timelogic
Average 90 stars, based on 1 article reviews
decypher ® accelerated hardware - by Bioz Stars, 2026-04
90/100 stars
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the decypher hardware accelerator  (Timelogic)
90
Timelogic the decypher hardware accelerator
The Decypher Hardware Accelerator, supplied by Timelogic, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/the decypher hardware accelerator/product/Timelogic
Average 90 stars, based on 1 article reviews
the decypher hardware accelerator - by Bioz Stars, 2026-04
90/100 stars
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mesh warp hardware accelerators  (Texas Instruments)
90
Texas Instruments mesh warp hardware accelerators
Mesh Warp Hardware Accelerators, supplied by Texas Instruments, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/mesh warp hardware accelerators/product/Texas Instruments
Average 90 stars, based on 1 article reviews
mesh warp hardware accelerators - by Bioz Stars, 2026-04
90/100 stars
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docchip hardware accelerator  (Xilinx Inc)
90
Xilinx Inc docchip hardware accelerator
The system-level architecture of the i <t>DocChip</t> binarization step.
Docchip Hardware Accelerator, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/docchip hardware accelerator/product/Xilinx Inc
Average 90 stars, based on 1 article reviews
docchip hardware accelerator - by Bioz Stars, 2026-04
90/100 stars
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hardware acceleration of adaptive neural networks (haana)  (Sandia National Laboratories)
90
Sandia National Laboratories hardware acceleration of adaptive neural networks (haana)
The system-level architecture of the i <t>DocChip</t> binarization step.
Hardware Acceleration Of Adaptive Neural Networks (Haana), supplied by Sandia National Laboratories, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/hardware acceleration of adaptive neural networks (haana)/product/Sandia National Laboratories
Average 90 stars, based on 1 article reviews
hardware acceleration of adaptive neural networks (haana) - by Bioz Stars, 2026-04
90/100 stars
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hardware accelerators  (RSA Security Inc)
90
RSA Security Inc hardware accelerators
The system-level architecture of the i <t>DocChip</t> binarization step.
Hardware Accelerators, supplied by RSA Security Inc, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/hardware accelerators/product/RSA Security Inc
Average 90 stars, based on 1 article reviews
hardware accelerators - by Bioz Stars, 2026-04
90/100 stars
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hardware accelerator eie  (Xilinx Inc)
90
Xilinx Inc hardware accelerator eie
The system-level architecture of the i <t>DocChip</t> binarization step.
Hardware Accelerator Eie, supplied by Xilinx Inc, used in various techniques. Bioz Stars score: 90/100, based on 1 PubMed citations. ZERO BIAS - scores, article reviews, protocol conditions and more
https://www.bioz.com/result/hardware accelerator eie/product/Xilinx Inc
Average 90 stars, based on 1 article reviews
hardware accelerator eie - by Bioz Stars, 2026-04
90/100 stars
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Image Search Results


The system-level architecture of the i DocChip binarization step.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip binarization step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

The system-level architecture of the i DocChip text and image segmentation step.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip text and image segmentation step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

The system-level architecture of the i DocChip text line extraction step.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip text line extraction step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

The system-level architecture of the i DocChip text line recognition step.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip text line recognition step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Hardware-software partitioning of the binarization process for the i DocChip system.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Hardware-software partitioning of the binarization process for the i DocChip system.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques: Software

Hardware-software partitioning of text and image segmentation for the i DocChip system.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Hardware-software partitioning of text and image segmentation for the i DocChip system.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques: Software

Hardware-software partitioning of text line extraction for the i DocChip system.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Hardware-software partitioning of text line extraction for the i DocChip system.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques: Software

The system-level architecture of the i DocChip binarization step.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip binarization step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

The system-level architecture of the i DocChip text line recognition step.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: The system-level architecture of the i DocChip text line recognition step.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Character-level accuracy of Cloud Vision OCR and i DocChip OCR.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Character-level accuracy of Cloud Vision OCR and i DocChip OCR.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Resource utilization of the hardware implementation for the end-to-end OCR i DocChip system (this work) compared to the total resource utilization of the previous separately implemented pipeline steps [ <xref ref-type= 26 , 27 , 28 , 29 ] using Zynq 7045 device @ 166MHz." width="100%" height="100%">

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Resource utilization of the hardware implementation for the end-to-end OCR i DocChip system (this work) compared to the total resource utilization of the previous separately implemented pipeline steps [ 26 , 27 , 28 , 29 ] using Zynq 7045 device @ 166MHz.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Power vs. runtime comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. Runtime is given per image. Single-threaded and multi-threaded implementations are represented as ST and MT . The grid lines show energy consumption in Joules (J).

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Power vs. runtime comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. Runtime is given per image. Single-threaded and multi-threaded implementations are represented as ST and MT . The grid lines show energy consumption in Joules (J).

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques:

Power vs. FPS comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. The grid lines show energy efficiency in FPS/W.

Journal: Journal of Imaging

Article Title: i DocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

doi: 10.3390/jimaging7090175

Figure Lengend Snippet: Power vs. FPS comparisons of the reference anyOCR and the optimized i DocChip algorithm on different platforms. The grid lines show energy efficiency in FPS/W.

Article Snippet: For the i DocChip hardware accelerator, the IP blocks of the operations offloaded to hardware are designed using Xilinx ® Vivado ® High-Level Synthesis version 2018.1.

Techniques: